1. Field of the Invention
This invention relates generally to the cell structure and fabrication process of vertical power transistors. More particularly, this invention relates to device ruggedness improvement and on resistance reduction by implementing a novel source contact structure and fabrication process.
2. Description of the Prior Art
For the purpose of improving the device ruggedness, limitations of higher fabrication cost and product reliability concerns still exist in the manufacture of power MOSFET transistors of shallower junctions. In order to achieve higher device ruggedness, a more complicate processes are often applied. These processes involve either the use of an extra implant mask to form a buried body implant region under the source region or the formation of spacer. The gate sidewall spacer is often applied which employs an oxide spacers to form the self aligned buried regions underneath the source regions with higher body-dopant concentration. In carring out the processing steps to form these oxide spacers, a special anisotropic etching process, e.g., a reactive ion etching (RIE), process is performed which often leads to special problems and limitations in manufacturing the power device. Leakage of the junction currents, directly below the space edges is often reported in device formed with oxide spacer. The problems can be attributed to silicon loss and spacer etch damages in the substrate which also lead to defects formed in the subsequent source implant and anneal. The performance of the power device and the reliability are therefore adversely affected due to these difficulties when spacers are implemented which are formed with these processing steps. Another problem is related to the gate oxide integrity. After the buried body implant, the oxide spacer is removed with a wet etch for subsequent source implant. The wet etch process results in cavities at the edge of the polysilicon gate. The cavities are not refilled during subsequent source diffusion process due to the time of diffusion is not sufficient to cause enough growth of the silicon oxide to refill the cavities. For high density MOSFET device, the cavities on edges of the gate is a more sever problem because a very short source diffusion is usually carried out to avoid deep junctions when longer source diffusion is performed.
In spite of these difficulties, a designer is nevertheless faced with a constant challenge to increase the device ruggedness due to the fact that various internal parasitic components often impose design and performance limitations on a conventional power metal oxide silicon field effect transistor (MOSFET). Among these parasitic components in a MOSFET transistor, special care must be taken in dealing with a parasitic npn bipolar junction transistor (BJT) formed between the source, the body, and the drain. Under normal static conditions the base and emitter of the parasitic BJT are shorted, leaving only the body-drain diode effective. However, in a transient conditions and during an avalanche breakdown, the parasitic BJT may be activated incidentally which can seriously degrade the overall performance of the MOSFET. Under the circumstances when the parasitic bipolar junction transistor is incidentally activated, snap back may occur which can cause permanent damages to the device. For this reason, precaution must be taken to increase the ruggedness of the device by taking into account that an incidental activation of the parasitic BJT should be prevented in an avalanche breakdown condition when large amount of hole current is generated in the core cell area.
In order to better understand the design issues related to device ruggedness encountered in the prior art, general descriptions for the structure of a conventional power MOSFET device and design issues relating to device ruggedness are first discussed. FIG. 1 shows a typical vertical double diffused MOS (VDMOS) device which uses a double diffusion technique to control the channel length l. Two successive diffusions are performed with first a p diffusion using boron, then a n diffusion using either arsenic or phosphorus, to produce two closely spaced pn junctions at different depths below the silicon surface. With this pn junction, as shown in FIG. 1, the VDMOS supports the drain voltage vertically in the n.sup.31 epitaxial layer. The current flows laterally from the source through the channel, parallel to the surface of the silicon. The current flow then turns through a right angle to flow vertically down through the drain epitaxial layer to the substrate and to the drain contact. The p-type "body" region in which the channel is formed when a sufficient positive voltage is applied to the gate. the channel length can be controlled through the processing steps. Because of the relative doping concentrations in the diffused p-channel region and the n- layer, the depletion layer which supports V.sub.DS, a drain to source voltage, extends down into the epitaxial layer rather than laterally into the channel. Under the circumstances of avalanche breakdown, a hole current, i.e., I.sub.h as shown in FIG. 1, is generated to flow from the breakdown region to the source. A voltage drop, I.sub.h R.sub.b, is generated over the parasitic NPN bipolar junction transistor as the hole current I.sub.h is transmitted via the p-body region underneath which has a p-body resistance R.sub.b. When this voltage drop across this parasitic bipolar junction transistor reaches a certain level, e.g., 0.7 volts, the parasitic bipolar transistor is turned on. Activation of the parasitic bipolar transistor, as discussed above, could cause snap-back and permanent damages to the MOSFET device.
For the purpose of improving the device ruggedness, Motorola discloses in Electronic Engineering Times, Apr. 8, 1996, Page 78, a HDTMOS-2 structure. In that structure, after the n.sup.+ source implant, a dielectric layer is grown on top of the polysilicon gate. The dielectric layer is etched to form the gate sidewall spacers for boron implant blocks, which are automatically self aligned with the source regions. This heavily doped p.sup.+ region underneath the source region can reduced the body to source resistance R.sub.b in the p-body region thus decreasing the voltage drop I.sub.h R.sub.b whereby the ruggedness of the MOSFET device is improved. However, additional difficulties arise from this spacer implementation. In order to fabricate the side-wall spacers, an anisotropic etch process is typically applied to remove the oxide in the flat areas while leaving the spacers at the side walls of the polysilicon gates. In order to account for variations in the spacer oxide layer thickness, some over etch is necessary. During the over-etch time, the field oxide and the silicon in the source or body junction regions may also be etched. Which may lead to the problems and difficulties discussed above. Furthermore, the uniformity of a reactive ion etch (RIE) process is difficult to control and the slope of the spacer may vary along the side-walls of the polysilicon gates. Which may then affect the self alignment and dopant profiles in subsequent ion implant operations to form the buried body-regions and the source regions. These difficulties in applying the RIE process cannot be easily resolved when the spacers are employed.
In order to reduce the body to source resistance, Korman et al. disclosed in U.S. Pat. No. 5,119,153 entitled "Small Cell Low Contact Resistance Rugged Power Field Effect Devices and Method of Fabrication" (issued on Jun. 2, 1992), a power field effect semiconductor device wherein an oxide or nitride spacer is used to form a heavily doped portion of a body region which is self aligned with respect to an aperture in the gate electrode. In forming the spacer, the nitride or oxide layer has to be formed and then anisotropically etched by reactive ion etching (RIE) in order to form the space along the side wall of the polysilicon silicon gate. Therefore, the device disclosed by Korman et al. is faced with the same technical difficulties associated with an-isotropic etching, such as an RIE process, as discussed above. Difficulties in manufacturability arising from imprecision of process control in applying this RIE method may also cause the cost of production to increase.
In yet another U.S. Pat. No. 5,268,586, entitled "Vertical Power MOS Device with Increased Ruggedness and Method of Fabrication", (issued on Dec. 7, 1993) Mukherjee et al. disclose a semiconductor device with improved ruggedness by forming a second body region, i.e., a second base region, within the first body region, under the source regions. As shown in a cross sectional view of FIG. 2A, the second body region is shallower than the first body region and is formed close to the channel region to reduce the parasitic resistance in the first body region. The lateral edges of the second body region are substantially aligned with the lateral edges of the gate electrode. The first body region and the source region are formed by sequential implantation through the polysilicon gate electrode using the polysfficon gate electrode as a self aligned mask. The second body region is then formed by body implantation, again, using the polysfficon gate as the implant mask, without substantial lateral diffusion. Since the second body region is formed without substantial lateral diffusion, very limited thermal budget is allowed for the this second body region. Reduction of the drain to source resistance is quite limited because, without enough diffusion process, this second body region is formed with reduced depth under the source regions. Furthermore, high contact resistance between the metal and the body region may occur due to a low P+ surface doping concentration as the net dopant concentration as a function of depth along the line F-F' shown in FIG. 2B. Additional difficulties of higher threshold voltage may also arise from lateral diffusion of the second body region to touch the channel region. Finally, a polysilicon layer of greater thickness employed in this structure may cause another problem. For high density DMOS device, poor metal coverage may occur when the re-firing of the thicker polysilicon layer to block the high energy body implant ions causes the contact openings to have high aspect ratio, i.e., high height to width ratio.
Therefore, there is still a need in the art of power device fabrication, particularly for power MOSFET design and fabrication, to provide a simplified and improved fabrication process that would resolve these limitations.